This application claims the benefit of the priority date of Korean Application No. 2002-28845, filed May 24, 2002.
The present invention relates to an integrated circuit in a semiconductor memory device for controlling impedance matching in the semiconductor memory device, and particularly to a semiconductor memory device for controlling on-die (on-chip) termination and further to a control circuit thereof.
CPUs, semiconductor memory devices, and gate arrays find application in electronic devices such as personal computers, servers, and workstations. In most cases, the devices include input pads and related circuits for inputting signals from an external source, and output pads and related circuits for outputting signals to an external source.
As the integration and speed of electronic devices increases, the swing width, or peak-to-peak voltage, of interface signals between the devices necessarily decreases. Reduction of swing width minimizes the time delay involved in signal transfer. However, as the swing width of signals is decreased, the influence of external noise on the signals also increases, and signal reflection from the receiving terminal becomes increasingly critical due to impedance mismatch. The impedance mismatch may be generated due to external noise, variation of the power supply, variation of the operating temperature, and variation in manufacturing process. If an impedance mismatch occurs, it is difficult to obtain high transfer speed in data transfer systems, and output data from output terminals of semiconductor memory devices may vary or may be unreliable, causing data transfer failure. In view of this, receiving terminals of devices are designed to include signal termination circuitry, referred to herein as on-chip termination or on-die termination, that mitigate impedance mismatch. Such impedance matching circuits and related circuits are located proximal to the input/output pads of the devices. At the transmitting end of a data transfer system, source termination is commonly employed, while at the receiving end, parallel termination is commonly employed.
Semiconductor memory devices such as DDR SDRAMs (Double Data Rate Synchronous Dynamic Random Access Memories) adopt termination circuits implemented with resistor units having a fixed value as illustrated in FIG. 1. FIG. 1 demonstrates a conventional arrangement for a termination circuit for terminating bonding pads in an integrated circuit (IC). Referring to FIG. 1, a plurality of input pads PD1, PD2, PD3, . . . are connected to a plurality of data nodes RD1, RD2, RD3 . . . via a plurality of termination circuits 10, 20, 30, . . . respectively.
FIG. 2 is a schematic illustration of a typical example of the termination circuit block BA1 of FIG. 1. The termination circuit 10 is comprised of resistors R1, R2 connected to the input pad PD1 of the receiver. Resistor R1 is connected to a power supply VDD, while resistor R2 is connected to ground VSS, An input circuit, such as an input buffer, may be connected to node RD1 in parallel with the termination circuit 10. In one example, if the termination circuit 10 is designed to have an parallel sum impedance value of 60 ohms, then the value of each resistor R1, R2 is 120 ohms.
The conventional on-chip termination circuit has a fixed value of resistor as shown in FIG. 2, and the impedance value therefore cannot be adjusted to compensate for variations in the external environment. Thus, a variable termination operation is not achieved by this configuration.
The present invention is directed to a system and method that allows for multiple modes of termination, including a fixed value that is preprogrammed, and a variable value that can, for example, be measured and determined by a self-calibration circuit. The present invention also provides for the possibility of multiple termination values within a single device. This is especially applicable to devices that have different loadings for address and data signals, for example in a configuration having a common, shared address bus, and multiple, localized data buses.
In one aspect, the present invention is directed to a control circuit for controlling the impedance of a pad termination comprising: a first input for inputting a variable impedance value; a second input for inputting a fixed impedance value; and a selector for selecting one of the fixed impedance value and the variable impedance value in response to a selection signal. The selector further outputs a selected impedance value to a pad termination circuit that provides the impedance of the pad termination in response to the selected impedance value.
The fixed impedance value may be generated in response to an open or closed state of a fuse, hard-wired state, or bonding state. The fixed impedance value may comprise a first fixed impedance value and third input may be provided for inputting a second fixed impedance value. In this case the selector selects one of the first fixed impedance value, the second fixed impedance value and the variable impedance value in response to the selection signal, and outputs the selected impedance value to the pad termination circuit.
A fourth input may be provided for inputting a deactivation impedance value, in which case the selector selects one of the fixed impedance value, the variable impedance value, and the deactivation impedance value in response to the selection signal, and outputs the selected impedance value to the pad termination circuit.
The pad termination circuit may apply the deactivation impedance value by removing the applied impedance. The selector may comprise a multiplexer. The variable impedance value may be generated by a self-calibration circuit.
The self-calibration circuit preferably comprises: a reference node that is coupled to a bonding pad having a reference impedance; a first comparator having a first input coupled to the reference node and a second input coupled to a reference voltage, the comparator comparing the first input and the second input to generate a comparison output; and a plurality of impedance loads in parallel between the reference node and a first reference voltage; the plurality of impedance loads being selectively activated in response to the comparison output to provide a combined impedance that substantially matches the reference impedance.
The first and second impedance values preferably comprise a plurality of binary bits. The pad termination circuit comprises a bank of resistors, individually selectable according to the binary bits of the first or second impedance values. The plurality of resistors have resistance values that are binary multiples of each other and are connected to a common node that is coupled to a bonding pad, and the impedance of the pad termination is determined by the combined selected resistance values.
The selected impedance value comprises a first selected impedance value and a second selector may be included for receiving the first selected impedance value, and for outputting a second selected impedance value to a second pad termination circuit that provides a second impedance of a second pad termination in response to the second selected impedance value. The second selected impedance value may be one of the same as the first selected impedance value, a multiple of the first selected impedance value, a deactivation value, or may be independent of the first selected impedance value. One of the first impedance value and second impedance value may be used for termination of one of data and address pads and the other of the first impedance value and second impedance value may be used for termination of the other of data and address pads.
At least one of the first and second selected impedance values may be further used for termination of command signal pads. The command signal pads may comprise pads for at least one of a chip select signal (CSB), a row address signal (RASB), a column address strobe signal (CASB) and a write enable signal (WEB).
The selection signal is preferably generated in response to a mode register set (MRS) command used for setting the operation mode of a memory device.
The impedance value may comprise pull-up and pull-down impedance values.
In another aspect, the present invention is directed to a control circuit for controlling the impedance of a pad termination at first and second circuit pads comprising a first circuit and a second circuit. The first circuit generates a first selected impedance value and comprises a first input for inputting a variable impedance value; second input for inputting a fixed impedance value; and a selector for selecting one of the first fixed impedance value and the variable impedance value in response to a selection signal, and for outputting a first selected impedance value to a first pad termination circuit that provides the impedance of the first circuit pad termination in response to the first selected impedance value. The second circuit generates a second selected impedance value and comprises: a third input for inputting the first selected impedance value; and a selector, in response to the first selected impedance value, for outputting a second selected impedance value to a second pad termination circuit that provides the impedance of the second pad termination in response to the second selected impedance value.
The second selected impedance value may be one of the same as the first selected impedance value, a multiple of the first selected impedance value, a deactivation value, or is independent of the first selected impedance value. The one of the first impedance value and second impedance value may be used for termination of one of data and address pads and the other of the first impedance value and second impedance value may be used for termination of the other of data and address pads.
The fixed impedance value may comprise a first fixed impedance value and the first circuit may further comprise a fourth input for inputting a second fixed impedance value, and wherein the selector selects one of the first fixed impedance value, the second fixed impedance value and the variable impedance value in response to the selection signal, and outputs the selected impedance value to the first pad termination circuit.
The first circuit may further comprises a fifth input for inputting a deactivation impedance value, in which case the selector may select one of the fixed impedance value, the variable impedance value, and the deactivation impedance value in response to the selection signal, and outputs the selected impedance value to the first pad termination circuit.
In another aspect, the present invention is directed to a method for controlling the impedance of a pad termination comprising: inputting a variable impedance value at a first input; inputting a fixed impedance value at a second input; and selecting one of the fixed impedance value and the variable impedance value in response to a selection signal, and outputting a selected impedance value to a pad termination circuit that provides the impedance of the pad termination in response to the selected impedance value.
In another aspect, the present invention is directed to a method for controlling the impedance of a pad termination at first and second circuit pads comprising: generating a first selected impedance value comprising: inputting a variable impedance value at a first input; inputting a fixed impedance value at a second input; and selecting one of the fixed impedance value and the variable impedance value in response to a selection signal, and outputting a first selected impedance value to a first pad termination circuit that provides the impedance of the first circuit pad termination in response to the first selected impedance value. A second selected impedance value is also generated, comprising: inputting the first selected impedance value at a third input; and outputting, in response to the first selected impedance value, a second selected impedance value to a second pad termination circuit that provides the impedance of the second pad termination in response to the second selected impedance value.